63 search results - page 8 / 13 » Wrapper design for embedded core test |
106
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VTS
2003
IEEE
15 years 7 months ago
2003
IEEE
Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimizati...
DATE
2000
IEEE
15 years 6 months ago
2000
IEEE
Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper in...
118
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DAC
2008
ACM
16 years 2 months ago
2008
ACM
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
ICCAD
2000
IEEE
15 years 6 months ago
2000
IEEE
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...
123
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VLSID
2008
IEEE
15 years 8 months ago
2008
IEEE
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...