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» XTR Implementation on Reconfigurable Hardware
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AHS
2006
IEEE
125views Hardware» more  AHS 2006»
15 years 12 months ago
Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs
Randomly connecting networks have proven to be universal computing machines. By interconnecting a set of nodes in a random way one can model very complicated non-linear dynamic sy...
Andres Upegui, Eduardo Sanchez
DSD
2006
IEEE
116views Hardware» more  DSD 2006»
15 years 12 months ago
Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard
This paper addresses the implementation of ReedSolomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB...
Arjan C. Dam, Michel G. J. Lammertink, Kenneth C. ...

Publication
266views
14 years 11 months ago
NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...
C. Farabet, B. Martini, B. Corda, P. Akselrod, E. ...
FPL
2006
Springer
156views Hardware» more  FPL 2006»
15 years 9 months ago
Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support
Advances in FPGA-based reconfigurable computers have made them a viable computing platform for a vast variety of computation demanding areas such as bioinformatics, speech recogni...
Hayden Kwok-Hay So, Robert W. Brodersen
DATE
2009
IEEE
159views Hardware» more  DATE 2009»
16 years 18 days ago
Design and implementation of a database filter for BLAST acceleration
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
Panagiotis Afratis, Constantinos Galanakis, Euripi...