34 search results - page 4 / 7 » Xtensa: A Configurable and Extensible Processor |
ICCAD
2001
IEEE
15 years 7 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
CSE
2008
IEEE
15 years 23 days ago
2008
IEEE
A well-known challenge during processor design is to obtain best possible results for a typical target application domain by combining flexibility and computational performance. A...
113
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TVLSI
2008
14 years 11 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
HPCA
2002
IEEE
15 years 11 months ago
2002
IEEE
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...
CODES
2007
IEEE
15 years 2 months ago
2007
IEEE
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...