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» Xtensa: A Configurable and Extensible Processor
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FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
15 years 4 months ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
15 years 5 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
OSDI
2002
ACM
15 years 11 months ago
Vertigo: Automatic Performance-Setting for Linux
Combining high performance with low power consumption is becoming one of the primary objectives of processor designs. Instead of relying just on sleep mode for conserving power, a...
Krisztián Flautner, Trevor N. Mudge
GECCO
2009
Springer
156views Optimization» more  GECCO 2009»
15 years 5 months ago
Characterizing the genetic programming environment for fifth (GPE5) on a high performance computing cluster
Solving complex, real-world problems with genetic programming (GP) can require extensive computing resources. However, the highly parallel nature of GP facilitates using a large n...
Kenneth Holladay
AINA
2007
IEEE
15 years 5 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...