17 search results - page 4 / 4 » Yield Improvement, Fault-Tolerance to the Rescue |
DAC
2011
ACM
12 years 6 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...