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ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
16 years 1 months ago
Three-Dimensional Cache Design Exploration Using 3DCacti
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, ...
ICCD
2007
IEEE
182views Hardware» more  ICCD 2007»
15 years 10 months ago
Reducing leakage power in peripheral circuits of L2 caches
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
Houman Homayoun, Alexander V. Veidenbaum
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
15 years 10 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
SKG
2006
IEEE
15 years 10 months ago
IAC: Interest-Aware Caching for Unstructured P2P
The simplicity and robustness of unstructured P2P system make it a preferable architecture for constructing real large scale file sharing system. Most of the existing paradigms re...
Xucheng Luo, Zhiguang Qin, Ji Geng, Jiaqing Luo
WMPI
2004
ACM
15 years 9 months ago
Addressing mode driven low power data caches for embedded processors
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
Ramesh V. Peri, John Fernando, Ravi Kolagotla