1000 search results - page 102 / 200 » Yield-Aware Cache Architectures |
136
click to vote
EUROMICRO
1998
IEEE
15 years 8 months ago
1998
IEEE
Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide issue processors due to the increasing penalties that w...
167
click to vote
LCTRTS
1999
Springer
15 years 8 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
163
click to vote
AGENTS
1997
Springer
15 years 8 months ago
1997
Springer
This paper presents a domain-independent architecture for facilitating visual problem solving between robots or softbots and humans. The architecture de nes virtual and human agen...
134
Voted
AINA
2004
IEEE
15 years 7 months ago
2004
IEEE
Streaming live video over peers in the Internet is gaining popularity since it has the advantage of reducing the load on the server and enable the server to perform other speciali...
120
Voted
APCSAC
2004
IEEE
15 years 7 months ago
2004
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...