Sciweavers

1000 search results - page 120 / 200
» Yield-Aware Cache Architectures
Sort
View
LCTRTS
2007
Springer
15 years 4 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
SIGCOMM
2009
ACM
15 years 4 months ago
Hash, don't cache: fast packet forwarding for enterprise edge routers
As forwarding tables and link speeds continue to grow, fast packet forwarding becomes increasingly challenging for enterprise edge routers. Simply building routers with ever large...
Minlan Yu, Jennifer Rexford
HPCA
2007
IEEE
15 years 4 months ago
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
Shared memory multiprocessors play an increasingly important role in enterprise and scientific computing facilities. Remote misses limit the performance of shared memory applicat...
Liqun Cheng, John B. Carter, Donglai Dai
ICDCSW
2002
IEEE
15 years 2 months ago
Class-Based Delta-Encoding: A Scalable Scheme for Caching Dynamic Web Content
Abstract—Caching static HTTP traffic in proxy-caches has reduced bandwidth consumption and download latency. However, web-caching performance is hard to increase further due to ...
Konstantinos Psounis
EDCC
2006
Springer
15 years 1 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...