1000 search results - page 121 / 200 » Yield-Aware Cache Architectures |
MICRO
1995
IEEE
15 years 1 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
130
click to vote
JNSM
2002
14 years 9 months ago
2002
Realizing high volume of data transmission in real time communication in a highly dynamic architecture like Mobile Ad hoc Networks (MANET) still remains a major point of research....
DAC
2009
ACM
15 years 11 months ago
2009
ACM
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictabilit...
RTSS
2007
IEEE
15 years 4 months ago
2007
IEEE
In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers a...
102
click to vote
HPCA
1998
IEEE
15 years 2 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...