1000 search results - page 122 / 200 » Yield-Aware Cache Architectures |
ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
MICRO
1998
IEEE
15 years 2 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
SIGGRAPH
1998
ACM
15 years 2 months ago
1998
ACM
We describe the clipmap, a dynamic texture representation that efficiently caches textures of arbitrarily large size in a finite amount of physical memory for rendering at real-...
DAC
1997
ACM
15 years 2 months ago
1997
ACM
Binary Decision Diagrams BDDs are e cient at manipulating large sets in a compact manner. BDDs, however, are inefcient at utilizing the memory hierarchy of the computer. Recent ...
HIPEAC
2009
Springer
15 years 1 months ago
2009
Springer
Abstract. On multi-core architectures with software-managed memories, effectively orchestrating data movement is essential to performance, but is tedious and error-prone. In this p...