1000 search results - page 123 / 200 » Yield-Aware Cache Architectures |
MICRO
2000
IEEE
14 years 9 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
ICC
2011
IEEE
13 years 9 months ago
2011
IEEE
Abstract—Content-Centric Networking is a new communication architecture that rethinks the Internet communication model, designed for point-to-point connections between hosts, and...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance ...
WWW
2003
ACM
15 years 10 months ago
2003
ACM
A modern approach for generating individualized web-sites is to compose a page out of individual elements, for instance XML-fragments, which is eventually transformed to . If the ...
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HPCA
2007
IEEE
15 years 10 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...