1000 search results - page 125 / 200 » Yield-Aware Cache Architectures |
ANCS
2007
ACM
15 years 1 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
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PDP
2010
IEEE
15 years 4 months ago
2010
IEEE
—This work presents a study undertaken to characterise the behaviour of some parallelisation techniques for irregular codes, previously developed for SMP architectures, on a seve...
MICRO
2005
IEEE
15 years 3 months ago
2005
IEEE
Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading)...
APCSAC
2003
IEEE
15 years 3 months ago
2003
IEEE
The StrongARM processor features virtually-addressed caches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB ...