Sciweavers

1000 search results - page 130 / 200
» Yield-Aware Cache Architectures
Sort
View
ANCS
2005
ACM
15 years 3 months ago
Architectural impact of stateful networking applications
The explosive and robust growth of the Internet owes a lot to the ”end-to-end principle”, which pushes stateful operations to the end-points. The Internet grew both in traffic...
Javier Verdú, Jorge García-Vidal, Ma...
IPPS
2000
IEEE
15 years 2 months ago
On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
Alberto Ferreira de Souza, Peter Rounce
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
15 years 6 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
15 years 6 months ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks
RTAS
2008
IEEE
15 years 4 months ago
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
Jack Whitham, Neil C. Audsley