1000 search results - page 137 / 200 » Yield-Aware Cache Architectures |
APCSAC
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the perform...
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
HPCA
1999
IEEE
15 years 2 months ago
1999
IEEE
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware...
MICRO
1999
IEEE
15 years 2 months ago
1999
IEEE
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...