Sciweavers

1000 search results - page 139 / 200
» Yield-Aware Cache Architectures
Sort
View
CASES
2007
ACM
15 years 1 months ago
An integrated ARM and multi-core DSP simulator
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
Sharad Singhai, MingYung Ko, Sanjay Jinturkar, May...
ICDCS
2010
IEEE
15 years 1 months ago
A Spinning Join That Does Not Get Dizzy
— As network infrastructures with 10 Gb/s bandwidth and beyond have become pervasive and as cost advantages of large commodity-machine clusters continue to increase, research and...
Philip Werner Frey, Romulo Goncalves, Martin L. Ke...
FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 1 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
CIKM
2006
Springer
15 years 1 months ago
Cache-oblivious nested-loop joins
We propose to adapt the newly emerged cache-oblivious model to relational query processing. Our goal is to automatically achieve an overall performance comparable to that of fine-...
Bingsheng He, Qiong Luo
CCGRID
2001
IEEE
15 years 1 months ago
QoS-Aware Discovery of Wide-Area Distributed Services
The global computational grids bring together distributed computation/communication resources. Beyond this, we envision the emergence of global `service grids', which provide...
Dongyan Xu, Klara Nahrstedt, Duangdao Wichadakul