1000 search results - page 146 / 200 » Yield-Aware Cache Architectures |
ISCA
2009
IEEE
15 years 4 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
CF
2009
ACM
15 years 4 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
SAINT
2008
IEEE
15 years 4 months ago
2008
IEEE
In the ubiquitous computing environment, we believe that P2P-based context-aware application utilizing sensing data is important. However, since sensors are not placed under the c...
IEEEPACT
2007
IEEE
15 years 4 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...