1000 search results - page 31 / 200 » Yield-Aware Cache Architectures |
147
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ISSS
2002
IEEE
15 years 9 months ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
108
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ICCD
2007
IEEE
16 years 29 days ago
2007
IEEE
As dual-core and quad-core processors arrive in the marketplace, the momentum behind CMP architectures continues to grow strong. As more and more cores/threads are placed on-die, ...
136
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HPCA
2005
IEEE
16 years 4 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
175
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ARCS
2012
Springer
13 years 11 months ago
2012
Springer
Abstract: In this paper, we present an acceleration method for texture-based ray casting on the compute unified device architecture (CUDA) compatible graphics processing unit (GPU...
138
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IEEEPACT
2006
IEEE
15 years 10 months ago
2006
IEEE
The role of the operating system (OS) in managing shared resources such as CPU time, memory, peripherals, and even energy is well motivated and understood [23]. Unfortunately, one...