1000 search results - page 34 / 200 » Yield-Aware Cache Architectures |
ISCA
2000
IEEE
15 years 1 months ago
2000
IEEE
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
68
Voted
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
SC
1992
ACM
15 years 1 months ago
1992
ACM
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
91
Voted
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...