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ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
15 years 3 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
ISLPED
2005
ACM
122views Hardware» more  ISLPED 2005»
15 years 3 months ago
A simple mechanism to adapt leakage-control policies to temperature
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...
Stefanos Kaxiras, Polychronis Xekalakis, Georgios ...
JNCA
2007
125views more  JNCA 2007»
14 years 9 months ago
Distributed middleware architectures for scalable media services
The fusion of Multimedia and Internet technology has introduced an ever-increasing demand for large-scale reliable media services. This exposes the scalability limitations of curr...
Vana Kalogeraki, Demetrios Zeinalipour-Yazti, Dimi...
ANCS
2009
ACM
14 years 7 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
MASCOTS
2008
14 years 11 months ago
Optimizing Galois Field Arithmetic for Diverse Processor Architectures and Applications
Galois field implementations are central to the design of many reliable and secure systems, with many systems implementing them in software. The two most common Galois field opera...
Kevin M. Greenan, Ethan L. Miller, Thomas J. E. Sc...