1000 search results - page 79 / 200 » Yield-Aware Cache Architectures |
143
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MICRO
2000
IEEE
14 years 9 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
101
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TCAD
2002
14 years 9 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
ICMCS
2005
IEEE
15 years 3 months ago
2005
IEEE
Recent technology advances in multimedia communication have ushered in a new era of personal communication. Users can ubiquitously access the Internet via various mobile devices. ...
SIGGRAPH
1999
ACM
15 years 2 months ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...