Sciweavers

1000 search results - page 87 / 200
» Yield-Aware Cache Architectures
Sort
View
ECRTS
2008
IEEE
15 years 4 months ago
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
15 years 3 months ago
PARLAK: Parametrized Lock Cache Generator
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
Bilge Saglam Akgul, Vincent John Mooney III
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
15 years 2 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
DATE
2008
IEEE
138views Hardware» more  DATE 2008»
15 years 4 months ago
Functional Self-Testing for Bus-Based Symmetric Multiprocessors
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adop...
Andreas Apostolakis, Dimitris Gizopoulos, Mihalis ...
PPOPP
1997
ACM
15 years 2 months ago
Performance Implications of Communication Mechanisms in All-Software Global Address Space Systems
Global addressing of shared data simplifies parallel programming and complements message passing models commonly found in distributed memory machines. A number of programming sys...
Beng-Hong Lim, Chi-Chao Chang, Grzegorz Czajkowski...