Sciweavers

1000 search results - page 94 / 200
» Yield-Aware Cache Architectures
Sort
View
SIGGRAPH
1994
ACM
15 years 1 months ago
FBRAM: a new form of memory optimized for 3D graphics
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
Michael F. Deering, Stephen A. Schlapp, Michael G....
DAMON
2006
Springer
15 years 1 months ago
Architecture-conscious hashing
Hashing is one of the fundamental techniques used to implement query processing operators such as grouping, aggregation and join. This paper studies the interaction between modern...
Marcin Zukowski, Sándor Héman, Peter...
ECOOP
1995
Springer
15 years 1 months ago
Do Object-Oriented Languages Need Special Hardware Support?
Previous studies have shown that object-oriented programs have different execution characteristics than procedural programs, and that special object-oriented hardware can improve p...
Urs Hölzle, David Ungar
MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
15 years 1 months ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin
CAL
2006
14 years 10 months ago
Performance modeling using Monte Carlo simulation
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck