711 search results - page 107 / 143 » Yield-aware placement optimization |
111
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ISPD
2003
ACM
15 years 8 months ago
2003
ACM
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
83
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ICCAD
2005
IEEE
16 years 5 days ago
2005
IEEE
Separate optimizations of logic and layout have been thoroughly studied in the past and are well documented for common benchmarks. However, to be competitive, modern circuit optim...
GECCO
2004
Springer
15 years 8 months ago
2004
Springer
This paper presents a study of the effectiveness of a recently presented crossover operator for the GAuGE system. This crossover, unlike the traditional crossover employed previou...
ICCAD
2000
IEEE
15 years 7 months ago
2000
IEEE
This paper proposes the concept of potential slack and show it is an effective metric of combinational circuit performance. We provide several methods for estimating potential sla...
123
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SAC
2010
ACM
15 years 3 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...