Sciweavers

711 search results - page 109 / 143
» Yield-aware placement optimization
Sort
View
IPPS
2006
IEEE
15 years 9 months ago
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
The development of Field Programmable Gate Arrays (FPGAs) had tremendous improvements in the last few years. They were extended from simple logic circuits to complex Systems-on-Ch...
Michael Hübner, Christian Schuck, Jürgen...
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
15 years 8 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...
SMA
2005
ACM
104views Solid Modeling» more  SMA 2005»
15 years 8 months ago
Packing a trunk: now with a twist!
In an industry project with a German car manufacturer we are faced with the challenge of placing a maximum number of uniform rigid rectangular boxes in the interior of a car trunk...
Friedrich Eisenbrand, Stefan Funke, Andreas Karren...
149
Voted
SLIP
2006
ACM
15 years 9 months ago
A tale of two nets: studies of wirelength progression in physical design
At every stage in physical design, engineers are faced with many different objectives and tools to develop, optimize, and evaluate their design. Each choice of a tool or an objec...
Andrew B. Kahng, Sherief Reda
ICCD
2004
IEEE
148views Hardware» more  ICCD 2004»
16 years 6 days ago
Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures
In this paper, we investigate the core-switch mapping(CSM) problem that optimally maps cores onto an NoC architecture such that either the energy consumption or the congestion is ...
Chan-Eun Rhee, Han-You Jeong, Soonhoi Ha