711 search results - page 129 / 143 » Yield-aware placement optimization |
DAC
2009
ACM
16 years 21 days ago
2009
ACM
In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing,...
109
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ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
ICCD
2003
IEEE
15 years 8 months ago
2003
IEEE
DNA probe arrays have recently emerged as one of the core genomic technologies. Exploiting analogies between manufacturing processes for DNA arrays and for VLSI chips, we demonstr...
125
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CVPR
2010
IEEE
15 years 8 months ago
2010
IEEE
In this paper, we deal with a generative model for multi-label, interactive segmentation. To estimate the pixel likelihoods for each label, we propose a new higher-order formulatio...
DCOSS
2009
Springer
15 years 6 months ago
2009
Springer
We consider dual classes of geometric coverage problems, in which disks, corresponding to coverage regions of sensors, are used to cover a region or set of points in the plane. The...