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» Yield-aware placement optimization
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DAC
2007
ACM
16 years 4 months ago
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs
In this paper, we present a new multi-packing tree (MP-tree) representation for macro placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient,...
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu...
EUROPAR
2001
Springer
15 years 7 months ago
Performance of High-Accuracy PDE Solvers on a Self-Optimizing NUMA Architecture
High-accuracy PDE solvers use multi-dimensional fast Fourier transforms. The FFTs exhibits a static and structured memory access pattern which results in a large amount of communic...
Sverker Holmgren, Dan Wallin
146
Voted
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
15 years 9 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
IPPS
2006
IEEE
15 years 9 months ago
Evaluating parallel simulated evolution strategies for VLSI cell placement
Simulated Evolution (SimE) is an evolutionary metaheuristic that has produced results comparable to well established stochastic heuristics such as SA, TS and GA, with shorter runti...
Sadiq M. Sait, Mustafa I. Ali, Ali Mustafa Zaidi
DAC
2004
ACM
15 years 8 months ago
Large-scale placement by grid-warping
Grid-warping is a new placement algorithm based on a strikingly simple idea: rather than move the gates to optimize their location, we elastically deform a model of the 2-0 chip s...
Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob ...