711 search results - page 62 / 143 » Yield-aware placement optimization |
125
Voted
ICC
2008
IEEE
15 years 9 months ago
2008
IEEE
—For the sake of maximizing the network lifetime, we propose a novel placement scheme for mobile data collectors in Underwater Acoustic Sensor Networks (UASNs). Our scheme is bas...
127
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ASPDAC
2005
ACM
15 years 9 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
154
Voted
DOCENG
2009
ACM
15 years 7 months ago
2009
ACM
We review the literature on automatic document formatting with an emphasis on recent work in the field. One common way to frame document formatting is as a constrained optimizatio...
121
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FPGA
1998
ACM
15 years 7 months ago
1998
ACM
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
105
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EURODAC
1994
IEEE
15 years 7 months ago
1994
IEEE
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...