711 search results - page 80 / 143 » Yield-aware placement optimization |
136
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ISVLSI
2007
IEEE
15 years 9 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
113
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CASES
2004
ACM
15 years 9 months ago
2004
ACM
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
137
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ISPD
2004
ACM
15 years 9 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
102
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HPCA
2006
IEEE
16 years 3 months ago
2006
IEEE
Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (retention tim...
139
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INFOCOM
2008
IEEE
15 years 9 months ago
2008
IEEE
Abstract—Recent advances in computer technology and wireless communications have enabled the emergence of stream-based sensor networks. In such sensor networks, real-time data ar...