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» Yield-aware placement optimization
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159
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INFOCOM
2006
IEEE
15 years 9 months ago
Relay Placement for Higher Order Connectivity in Wireless Sensor Networks
Abstract— Sensors typically use wireless transmitters to communicate with each other. However, sensors may be located in a way that they cannot even form a connected network (e.g...
Abhishek Kashyap, Samir Khuller, Mark A. Shayman
PODC
2005
ACM
15 years 9 months ago
Quorum placement in networks to minimize access delays
A quorum system is a family of sets (themselves called quorums), each pair of which intersect. In many distributed algorithms, the basic unit accessed by a client is a quorum of n...
Anupam Gupta, Bruce M. Maggs, Florian Oprea, Micha...
ICCAD
1998
IEEE
101views Hardware» more  ICCAD 1998»
15 years 7 months ago
Wireplanning in logic synthesis
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alb...
137
Voted
ASPDAC
1998
ACM
160views Hardware» more  ASPDAC 1998»
15 years 7 months ago
Synthesis of Power Efficient Systems-on-Silicon
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...
DAC
1997
ACM
15 years 7 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling