2 search results - page 1 / 1 » Yield-constrained digital circuit sizing via sequential geom... |
138
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ISQED
2010
IEEE
15 years 7 months ago
2010
IEEE
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
166
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ISQED
2005
IEEE
15 years 10 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...