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» Zero overhead watermarking technique for FPGA designs
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ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
15 years 6 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...
SIGOPS
2008
116views more  SIGOPS 2008»
14 years 9 months ago
Practical techniques for purging deleted data using liveness information
The layered design of the Linux operating system hides the liveness of file system data from the underlying block layers. This lack of liveness information prevents the storage sy...
David Boutcher, Abhishek Chandra
DDECS
2007
IEEE
143views Hardware» more  DDECS 2007»
15 years 3 months ago
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for dupl...
Pavel Kubalík, Jirí Kvasnicka, Hana ...
DFT
1999
IEEE
125views VLSI» more  DFT 1999»
15 years 1 months ago
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
John Lach, William H. Mangione-Smith, Miodrag Potk...
DAC
2003
ACM
15 years 10 months ago
Compiler-generated communication for pipelined FPGA applications
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz