35 search results - page 7 / 7 » Zero overhead watermarking technique for FPGA designs |
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
INFOCOM
2009
IEEE
15 years 4 months ago
2009
IEEE
—Network protocols have traditionally been designed using a layered method in part because it is easier to implement some portions of network protocols in software and other port...
ASPLOS
2011
ACM
14 years 1 months ago
2011
ACM
The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware...