49 search results - page 3 / 10 » Zero-content augmented caches |
84
Voted
IEEEPACT
2007
IEEE
15 years 3 months ago
2007
IEEE
Distinguishing transient blocks from frequently used blocks enables servicing references to transient blocks from a small fully-associative auxiliary cache structure. By inserting...
TC
2008
14 years 9 months ago
2008
Abstract--Today's storage systems place an imperative demand on energy efficiency. A storage system often places single-rotationrate disks into standby mode by stopping them f...
80
Voted
ISCA
1998
IEEE
15 years 1 months ago
1998
IEEE
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...
97
Voted
HIPEAC
2010
Springer
14 years 11 months ago
2010
Springer
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...
83
Voted
ISCA
2000
IEEE
15 years 1 months ago
2000
IEEE
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...