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ASAP
2006
IEEE
119views Hardware» more  ASAP 2006»
13 years 8 months ago
From Bit Level Systolic Arrays to HDTV Processor Chips
The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on sys...
John V. McCanny, Roger F. Woods, John G. McWhirter
ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
13 years 10 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
ASAP
2006
IEEE
108views Hardware» more  ASAP 2006»
13 years 10 months ago
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
Pablo Ituero, Marisa López-Vallejo
ASAP
2006
IEEE
114views Hardware» more  ASAP 2006»
13 years 10 months ago
The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines
Early FPGA researchers understood that FPGAs made possible the creation of a new, flexible, and powerful class of machine -- the configurable computing machine (CCM). The earliest...
Brent E. Nelson
ASAP
2006
IEEE
109views Hardware» more  ASAP 2006»
14 years 10 days ago
Describing Quantum Circuits with Systolic Arrays
In the simulation of quantum circuits the matrices and vectors used to represent unitary operations and qubit states grow exponentially as the number of qubits increase. For insta...
Aasavari Bhave, Eurípides Montagne, Edgar G...