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ASPDAC
2006
ACM
103views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Prefetching-aware cache line turnoff for saving leakage energy
Abstract— While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This paper studies this i...
Ismail Kadayif, Mahmut T. Kandemir, Feihui Li
ASPDAC
2000
ACM
159views Hardware» more  ASPDAC 2000»
15 years 2 months ago
Analytical minimization of half-perimeter wirelength
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
Andrew A. Kennings, Igor L. Markov
ASPDAC
2000
ACM
97views Hardware» more  ASPDAC 2000»
15 years 2 months ago
Symbolic debugging of globally optimized behavioral specifications
Symbolic debuggers are system development tools that can accelerate the validation speed of behavioral specifications by allowing a user to interact with an executing code at the ...
Inki Hong, Darko Kirovski, Miodrag Potkonjak, Mari...
ASPDAC
2000
ACM
117views Hardware» more  ASPDAC 2000»
15 years 2 months ago
Improved algorithms for hypergraph bipartitioning
Multilevel Fiduccia-Mattheyses MLFM hypergraph partitioning 3, 22, 24 is a fundamental optimization in VLSI CAD physical design. The leading implementation, hMetis 23 , has sinc...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
ASPDAC
2000
ACM
111views Hardware» more  ASPDAC 2000»
15 years 2 months ago
Gate-level aged timing simulation methodology for hot-carrier reliability assurance
- This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a un...
Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezaw...