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ASPDAC
2005
ACM
123views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Comparing high-level modeling approaches for embedded system design
- This paper presents a comparison between three different high-level modeling approaches for embedded systems design, focusing on systems that require dataflow models. The propose...
Lisane B. de Brisolara, Leandro Buss Becker, Luigi...
ASPDAC
2005
ACM
65views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Library cell layout with Alt-PSM compliance and composability
The sustained miniaturization of VLSI feature size presents great challenges to sub-wavelength photolithography and requests usage of many Resolution Enhancement Techniques (RET)....
Ke Cao, Puneet Dhawan, Jiang Hu
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ASPDAC
2005
ACM
193views Hardware» more  ASPDAC 2005»
15 years 3 months ago
VLSI on-chip power/ground network optimization considering decap leakage currents
- In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, ...
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
15 years 3 months ago
System-level communication modeling for network-on-chip synthesis
— As we are entering the network-on-chip era and system communication is becoming a dominating factor, comon abstraction and synthesis are becoming the integral part of system de...
Andreas Gerstlauer, Dongwan Shin, Rainer Döme...
ASPDAC
2005
ACM
91views Hardware» more  ASPDAC 2005»
14 years 11 months ago
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem
-- This paper presents a novel global routing algorithm, AT-PO-GR, to minimize the routing area under both congestion, timing, and RLC crosstalk constraints. The proposed algorithm...
Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, ...