New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the re...
Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, M...
Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...
- We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, ...
— The customization of architectures in designing the security processor-based systems typically involves timeconsuming simulation and sophisticated analysis in the exploration o...
In order to handle device matching for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis. In this paper, we deal with the module...