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ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Standard CMOS technology on-chip inductors with pn junctions substrate isolation
New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the re...
Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, M...
ASPDAC
2005
ACM
79views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...
Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-...
ASPDAC
2005
ACM
96views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Oscillation ring based interconnect test scheme for SOC
- We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, ...
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
14 years 11 months ago
System-level design space exploration for security processor prototyping in analytical approaches
— The customization of architectures in designing the security processor-based systems typically involves timeconsuming simulation and sophisticated analysis in the exploration o...
Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee
ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Placement with symmetry constraints for analog layout design using TCG-S
In order to handle device matching for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis. In this paper, we deal with the module...
Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hu...