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ASPDAC
2005
ACM
131views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Analysis of buffered hybrid structured clock networks
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld...
ASPDAC
2004
ACM
149views Hardware» more  ASPDAC 2004»
15 years 3 months ago
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design
With the exponential reduction in the scaling of feature size, inter-wire coupling capacitance becomes the dominant part of load capacitance. Two problems are introduced by coupli...
Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, J...
ASPDAC
2005
ACM
106views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Using loop invariants to fight soft errors in data caches
Ever scaling process technology makes embedded systems more vulnerable to soft errors than in the past. One of the generic methods used to fight soft errors is based on duplicati...
Sri Hari Krishna Narayanan, Seung Woo Son, Mahmut ...
ASPDAC
2005
ACM
140views Hardware» more  ASPDAC 2005»
15 years 3 months ago
A multi-level transmission line network approach for multi-giga hertz clock distribution
-In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and m...
Hongyu Chen, Chung-Kuan Cheng
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ASPDAC
2005
ACM
99views Hardware» more  ASPDAC 2005»
14 years 11 months ago
A fast counterexample minimization approach with refutation analysis and incremental SAT
- It is a hotly research topic to eliminate irrelevant variables from counterexample, to make it easier to be understood. BFL algorithm is the most effective Counterexample minim...
ShengYu Shen, Ying Qin, Sikun Li