Abstract— As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unus...
Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykr...
Abstract— This paper proposes an approach to cope with temporal power/ground voltage fluctuation for static timing analysis. The proposed approach replaces temporal noise with a...
— We present SoCExplore, a framework for fast communicationcentric design space exploration of complex SoCs with networkbased interconnects. Speed-up in exploration is achieved t...
- This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology and system-on-chip have resulted in a considerable portion of power consumpti...
Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, H...
- This paper extends the depth first search (DFS) used in the previously proposed witness string method for generating efficient test vectors. A state pruning method is added that ...