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ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
Dan Zhao, Unni Chandran, Hideo Fujiwara
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Fast Buffer Insertion for Yield Optimization Under Process Variations
With the emerging process variations in fabrication, the traditional corner-based timing optimization techniques become prohibitive. Buffer insertion is a very useful technique fo...
Ruiming Chen, Hai Zhou
ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan
ASPDAC
2007
ACM
92views Hardware» more  ASPDAC 2007»
15 years 2 months ago
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Ma...
Ruiming Chen, Hai Zhou
ASPDAC
2007
ACM
135views Hardware» more  ASPDAC 2007»
15 years 2 months ago
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
- Most image processing applications are computationally intensive and data intensive. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these a...
Yazhuo Dong, Yong Dou