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ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
15 years 2 months ago
PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool
- This paper presents a simulation tool targeted specifically at bang-bang type phase locked loop systems. The aim of this simulator is to quickly and accurately predict important ...
Michael Chan, Adam Postula, Yong Ding
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect
Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper int...
Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud
ASPDAC
2007
ACM
102views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...
Chuan Lin, Hai Zhou
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Logic and Layout Aware Voltage Island Generation for Low Power Design
Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but...
Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
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ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...
Marc Boule, Zeljko Zilic