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87
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ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Safe Delay Optimization for Physical Synthesis
-- Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the final result, often by neg...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
89
Voted
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Optimization of Arithmetic Datapaths with Finite Word-Length Operands
Abstract: This paper presents an approach to area optimization of arithmetic datapaths that perform polynomial computations over bit-vectors with finite widths. Examples of such de...
Sivaram Gopalakrishnan, Priyank Kalla, Florian Ene...
ASPDAC
2007
ACM
109views Hardware» more  ASPDAC 2007»
15 years 2 months ago
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
Abstract-- With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-dr...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
ASPDAC
2007
ACM
137views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Delay Uncertainty Reduction by Interconnect and Gate Splitting
Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective sp...
Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet...
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...