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    ASPDAC
    2009
    ACM
    122views Hardware» more  ASPDAC 2009»
    Tolerating process variations in high-level synthesis using transparent latches
    15 years 5 months ago
    Tolerating process variations in high-level synthesis using transparent latches
    Download  www.cse.psu.edu
    —Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
    Yibo Chen, Yuan Xie
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    ASPDAC
    2009
    ACM
    212views Hardware» more  ASPDAC 2009»
    Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
    15 years 5 months ago
    Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
    Download  vlsicad.ucsd.edu
    Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
    Kwangok Jeong, Andrew B. Kahng
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    ASPDAC
    2009
    ACM
    164views Hardware» more  ASPDAC 2009»
    Accounting for non-linear dependence using function driven component analysis
    15 years 4 months ago
    Accounting for non-linear dependence using function driven component analysis
    Download  eda.ee.ucla.edu
    Majority of practical multivariate statistical analyses and optimizations model interdependence among random variables in terms of the linear correlation among them. Though linear...
    Lerong Cheng, Puneet Gupta, Lei He
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    ASPDAC
    2009
    ACM
    152views Hardware» more  ASPDAC 2009»
    A control theory approach for thermal balancing of MPSoC
    15 years 5 months ago
    A control theory approach for thermal balancing of MPSoC
    Download  infoscience.epfl.ch
    — Thermal balancing and reducing hot-spots are two important challenges facing the MPSoC designers. In this work, we model the thermal behavior of a MPSoC as a control theory pro...
    Francesco Zanini, David Atienza, Giovanni De Miche...
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    ASPDAC
    2009
    ACM
    127views Hardware» more  ASPDAC 2009»
    Timing driven power gating in high-level synthesis
    15 years 5 months ago
    Timing driven power gating in high-level synthesis
    Download  rd.cycu.edu.tw
    - The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
    Shih-Hsu Huang, Chun-Hua Cheng
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