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    Gate-level modelling and verification of asynchronous circuits using CSPM and FDR
    16 years 16 days ago
    Gate-level modelling and verification of asynchronous circuits using CSPM and FDR
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    Mark B. Josephs
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    Demystifying Data-Driven and Pausible Clocking Schemes
    16 years 16 days ago
    Demystifying Data-Driven and Pausible Clocking Schemes
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    Robert D. Mullins, Simon W. Moore
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    A Configurable Asynchronous Pseudorandom Bit Sequence Generator
    16 years 16 days ago
    A Configurable Asynchronous Pseudorandom Bit Sequence Generator
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    Alex Chow, William S. Coates, David Hopkins
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    A Jitter Attenuating Timing Chain
    16 years 16 days ago
    A Jitter Attenuating Timing Chain
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    Suwen Yang, Mark R. Greenstreet, Jihong Ren
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    2007
    IEEE
    97views Hardware» more  ASYNC 2007»
    A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability
    16 years 16 days ago
    A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability
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    Nikolaos Minas, David Kinniment, Keith Heron, Gord...
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