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DSD
2005
IEEE
75views Hardware» more  DSD 2005»
15 years 6 months ago
An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform
We describe a new e-learning environment and a runtime platform for educational tools on digital system testing and design for testability. This environment is being developed in ...
Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogub...
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
15 years 6 months ago
Utilizing don't care states in SAT-based bounded sequential problems
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
Sean Safarpour, Görschwin Fey, Andreas G. Ven...
ISMAR
2005
IEEE
15 years 5 months ago
Adaptive Line Tracking with Multiple Hypotheses for Augmented Reality
We present a real-time model-based line tracking approach with adaptive learning of image edge features that can handle partial occlusion and illumination changes. A CAD (VRML) mo...
Harald Wuest, Florent Vial, Didier Stricker
VLSID
2005
IEEE
97views VLSI» more  VLSID 2005»
15 years 5 months ago
Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs
In recent years, there has been an increasing interest in Quantified Boolean Formula (QBF) evaluation, since several VLSI CAD problems can be formulated efficiently as QBF insta...
Kameshwar Chandrasekar, Michael S. Hsiao
ISLPED
2005
ACM
91views Hardware» more  ISLPED 2005»
15 years 5 months ago
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
Hassan Hassan, Mohab Anis, Mohamed I. Elmasry