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CASES
2001
ACM
15 years 1 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
CASES
2001
ACM
15 years 1 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic
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CASES
2001
ACM
15 years 1 months ago
The very portable optimizer for digital signal processors
Although retargetability has been a major design concern for many compilers, retargetability is a vitally important issue for Digital Signal Processors(DSPs) because the architect...
Sungjoon Jung, Yunheung Paek
CASES
2001
ACM
15 years 1 months ago
The emerging power crisis in embedded processors: what can a poor compiler do?
It is widely acknowledged that even as VLSI technology advances, there is a looming crisis that is an important obstacle to the widespread deployment of mobile embedded devices, n...
Lakshmi N. Chakrapani, Pinar Korkmaz, Vincent John...
CASES
2001
ACM
15 years 1 months ago
Combined partitioning and data padding for scheduling multiple loop nests
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu