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TVLSI
2008
187views more  TVLSI 2008»
14 years 11 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
TWC
2008
154views more  TWC 2008»
14 years 11 months ago
MEERA: Cross-Layer Methodology for Energy Efficient Resource Allocation in Wireless Networks
Abstract-- In many portable devices, wireless network interfaces consume upwards of 30% of scarce system energy. Reducing the transceiver's power consumption to extend the sys...
Sofie Pollin, Rahul Mangharam, Bruno Bougard, Lies...
TWC
2008
120views more  TWC 2008»
14 years 11 months ago
Binary Power Control for Sum Rate Maximization over Multiple Interfering Links
We consider allocating the transmit powers for a wireless multi-link (N-link) system, in order to maximize the total system throughput under interference and noise impairments, and...
Anders Gjendemsjø, David Gesbert, Geir E. &...
VLC
2008
191views more  VLC 2008»
14 years 11 months ago
Visual specification of measurements and redesigns for domain specific visual languages
Ensuring model quality is a key success factor in many computer science areas, and becomes crucial in recent software engineering paradigms like the one proposed by model-driven s...
Esther Guerra, Juan de Lara, Paloma Díaz
VLSISP
2008
104views more  VLSISP 2008»
14 years 11 months ago
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Data dominated signal processing applications are typically described using large and multi-dimensional arrays and loop nests. The order of production and consumption of array ele...
Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verd...