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CDES
2006
101views Hardware» more  CDES 2006»
13 years 7 months ago
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors
- Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the latency and coverage. In this paper, a ne...
Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin
CDES
2006
136views Hardware» more  CDES 2006»
13 years 7 months ago
CMOL FPGA circuits
Abstract--This paper describes an architecture of FPGAlike fabric for future hybrid "CMOL" circuits. Such circuits will combine a semiconductor-transistor (CMOS) stack an...
Dmitri B. Strukov, Konstantin Likharev
CDES
2006
184views Hardware» more  CDES 2006»
13 years 7 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
CDES
2006
118views Hardware» more  CDES 2006»
13 years 7 months ago
New DSP Benchmark based on Selectable Mode Vocoder (SMV)
Digital signal processing (DSP) industry has been growing rapidly over the past few years; it remains the technology driver for the recovering semiconductor industry. Performance ...
Erh-Wen Hu, Cyril Ku, Andrew Russo, Bogong Su, Jia...
CDES
2006
98views Hardware» more  CDES 2006»
13 years 7 months ago
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer
Recently, several loop buffer designs have been proposed to reduce instruction fetch energy due to size and location advantage of loop buffer. Nevertheless, on design complexity di...
Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung