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    SIP
    2003
    121views Image Processing» more  SIP 2003»
    Code-aided Phase and Timing Ambiguity Resolution for AWGN Channels
    14 years 11 months ago
    Code-aided Phase and Timing Ambiguity Resolution for AWGN Channels
    Download  telin.ugent.be
    We present a novel maximum-likelihood (ML) joint frame synchronization and carrier phase ambiguity resolution algorithm for coded systems that exploits the code properties by acce...
    Henk Wymeersch, Marc Moeneclaey
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    69
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    GECCO
    2003
    Springer
    117views Optimization» more  GECCO 2003»
    Uniform Crossover Revisited: Maximum Disruption in Real-Coded GAs
    15 years 2 months ago
    Uniform Crossover Revisited: Maximum Disruption in Real-Coded GAs
    Download  www.cs.york.ac.uk
    A detailed comparison is presented of five well-known crossover operators on a range of continuous optimization tasks to test longheld beliefs concerning disruption, with respect ...
    Stephen Drake
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    84
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    WORM
    2003
    220views Security Privacy» more  WORM 2003»
    Detection of injected, dynamically generated, and obfuscated malicious code
    14 years 11 months ago
    Detection of injected, dynamically generated, and obfuscated malicious code
    Download  www.ll.mit.edu
    This paper presents DOME, a host-based technique for detecting several general classes of malicious code in software executables. DOME uses static analysis to identify the locatio...
    Jesse C. Rabek, Roger I. Khazan, Scott M. Lewandow...
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    72
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    DFT
    2003
    IEEE
    117views VLSI» more  DFT 2003»
    Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
    15 years 2 months ago
    Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
    Download  www.eng.yale.edu
    We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
    Sobeeh Almukhaizim, Yiorgos Makris
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    IOLTS
    2003
    IEEE
    124views Hardware» more  IOLTS 2003»
    Designing FPGA based Self-Testing Checkers for m-out-of-n Codes
    15 years 2 months ago
    Designing FPGA based Self-Testing Checkers for m-out-of-n Codes
    Download  www.tau.ac.il
    The paper describes a specific method for designing selfchecking checkers for m-out-of-n codes. The method is oriented to the Field Programmable Gate Arrays technology and is base...
    A. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. N...
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