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CODES
2004
IEEE
15 years 2 months ago
A novel deadlock avoidance algorithm and its hardware implementation
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
Jaehwan Lee, Vincent John Mooney III
CODES
2004
IEEE
15 years 2 months ago
Facilitating reuse in hardware models with enhanced type inference
High-level hardware modeling is an essential, yet time-consuming, part of system design. However, effective component-based reuse in hardware modeling languages can reduce model c...
Manish Vachharajani, Neil Vachharajani, Sharad Mal...
CODES
2004
IEEE
15 years 2 months ago
CPU scheduling for statistically-assured real-time performance and improved energy efficiency
We present a CPU scheduling algorithm, called Energy-efficient Utility Accrual Algorithm (or EUA), for battery-powered, embedded real-time systems. We consider an embedded softwar...
Haisang Wu, Binoy Ravindran, E. Douglas Jensen, Pe...
CODES
2004
IEEE
15 years 2 months ago
Benchmark-based design strategies for single chip heterogeneous multiprocessors
Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs trad...
JoAnn M. Paul, Donald E. Thomas, Alex Bobrek
CODES
2004
IEEE
15 years 2 months ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...